[PATCH] irqchip/sifive-plic: default to enabled

[Conor Dooley]

From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

The SiFive PLIC driver is used by all current implementations, including
those that do not have a SiFive PLIC. Default the driver to enabled,
with the intention of later removing the current "every SOC selects
this" situation in Kconfig.socs at the moment.

The speculative "potential others" in the description no longer makes
any sense, as the driver is always used. Update the Kconfig symbol's
description to reflect the driver's ubiquitous state.

Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
Hey Marc,

I recall some discussion when this driver was extended to other PLICs a
few months ago:
https://lore.kernel.org/linux-riscv/20511a05f39408c8ffbcc98923c4abd2@xxxxxxxxxx/

Perhaps I got the wrong impression, but it seemed to me that you intend
for future implementations to reuse this driver where possible?

I'd like to think, and surely will be proven wrong, that ~all future
plic implementations should be similar enough to fit that bill.
It's kinda on this basis that I figure switching this thing to default y
should be okay. It's already only buildable on RISC-V & every
implementation uses it, so no difference there.

Thanks,
Conor.
---
 drivers/irqchip/Kconfig | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7ef9f5e696d3..6f99919ba66c 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -553,14 +553,15 @@ config RISCV_INTC
 config SIFIVE_PLIC
 	bool "SiFive Platform-Level Interrupt Controller"
 	depends on RISCV
+	default y
 	select IRQ_DOMAIN_HIERARCHY
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
 	help
-	   This enables support for the PLIC chip found in SiFive (and
-	   potentially other) RISC-V systems.  The PLIC controls devices
-	   interrupts and connects them to each core's local interrupt
-	   controller.  Aside from timer and software interrupts, all other
-	   interrupt sources are subordinate to the PLIC.
+	   This enables support for the PLIC chip found in SiFive & other
+	   RISC-V systems.  The PLIC controls devices interrupts and connects
+	   them to each core's local interrupt controller.  Aside from timer
+	   and software interrupts, all other interrupt sources are
+	   subordinate to the PLIC.
 
 	   If you don't know what to do here, say Y.
 
-- 
2.37.2