Re: WARNING: CPU: 0 PID: 0 at arch/x86/include/asm/kfence.h:46 kfence_protect

[Dave Hansen]

On 11/17/22 15:23, Marco Elver wrote:
> Yes - it's the 'level != PG_LEVEL_4K'.

That plus the bisect made it pretty easy to find, thanks for the effort!

Could you double-check that the attached patch fixes it?  It seemed to
for me.

The issue was that the new "No changes, easy!" check in the suspect
commit didn't check the cpa->force_split option.  It didn't split down
to 4k and then all hell broke loose.

Oh, and I totally misread the kfence ability to tolerate partial TLB
flushes.  Sorry for the noise there!
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 220361ceb997..9b4e2ad957f6 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -1727,7 +1727,8 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int primary)
 	/*
 	 * No changes, easy!
 	 */
-	if (!(pgprot_val(cpa->mask_set) | pgprot_val(cpa->mask_clr)))
+	if (!(pgprot_val(cpa->mask_set) | pgprot_val(cpa->mask_clr))
+	    && !cpa->force_split)
 		return ret;
 
 	while (rempages) {