Re: [PATCH v2] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations
From: Marcel Ziswiler
Date: Fri Nov 18 2022 - 05:48:09 EST
Hi Richard
On Fri, 2022-11-18 at 10:56 +0800, Richard Zhu wrote:
> Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> i.MX8MP PCIe reference clock.
>
> The following properties of PHY dts node should be changed accordingly.
> - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_AXI>'.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
Tested-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
This works perfectly fine on Verdin iMX8M Plus as well. I will update my previous PCIe-enablement commit
(device tree part) in that respect and (re-)submit it.
Thanks!
Cheers
Marcel
> ---
> v1->v2:
> Refer to Lucas' comments, don't expose IMX8MP_CLK_HSIO_ROOT to dts node.
> https://patchwork.ozlabs.org/project/linux-pci/patch/1666590189-1364-1-git-send-email-hongxing.zhu@xxxxxxx/
>
> Use <&clk IMX8MP_CLK_HSIO_AXI> as referrence clock source when internal
> clock mode is used by i.MX8MP PCIe module.
>
> Verified on i.MX8MP EVK board with removing R131/R132/R137/R138, and
> populating R135/R136.
> ---
> drivers/soc/imx/imx8mp-blk-ctrl.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
> index 0e3b6ba22f94..5ad20a8ea25e 100644
> --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -21,6 +21,16 @@
> #define USB_CLOCK_MODULE_EN BIT(1)
> #define PCIE_PHY_APB_RST BIT(4)
> #define PCIE_PHY_INIT_RST BIT(5)
> +#define GPR_REG2 0x8
> +#define P_PLL_MASK GENMASK(5, 0)
> +#define M_PLL_MASK GENMASK(15, 6)
> +#define S_PLL_MASK GENMASK(18, 16)
> +#define P_PLL (0xc << 0)
> +#define M_PLL (0x320 << 6)
> +#define S_PLL (0x4 << 16)
> +#define GPR_REG3 0xc
> +#define PLL_CKE BIT(17)
> +#define PLL_RST BIT(31)
>
> struct imx8mp_blk_ctrl_domain;
>
> @@ -86,6 +96,18 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
> case IMX8MP_HSIOBLK_PD_PCIE_PHY:
> regmap_set_bits(bc->regmap, GPR_REG0,
> PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
> +
> + /* Set the PLL configurations, P = 12, M = 800, S = 4. */
> + regmap_update_bits(bc->regmap, GPR_REG2,
> + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
> + P_PLL | M_PLL | S_PLL);
> + udelay(1);
> +
> + regmap_update_bits(bc->regmap, GPR_REG3, PLL_RST, PLL_RST);
> + udelay(10);
> +
> + /* Set 1b'1 to pll_cke of GPR_REG3 */
> + regmap_update_bits(bc->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
> break;
> default:
> break;