Re: [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N

[Ian Rogers]

On Thu, Nov 17, 2022 at 11:56 PM <zhengjun.xing@xxxxxxxxxxxxxxx> wrote:
>
> From: Zhengjun Xing <zhengjun.xing@xxxxxxxxxxxxxxx>
>
> Alderlake-N only has E-core, it has been moved to non-hybrid code path on
> the kernel side, add the cpuid for Alderlake-N separately. Both events for
> Alderlake and Alderlake-N are based on JSON file v1.16.

The update to 1.16 is true at the end of the patch series rather than
the beginning. It makes more sense to bump the version in the same
change that updates the json otherwise reverting the json changes
leaves the version number in place.

Thanks,
Ian


> Signed-off-by: Zhengjun Xing <zhengjun.xing@xxxxxxxxxxxxxxx>
> Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> ---
>  tools/perf/pmu-events/arch/x86/mapfile.csv | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
> index 5e609b876790..df47462a125f 100644
> --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> @@ -1,5 +1,6 @@
>  Family-model,Version,Filename,EventType
> -GenuineIntel-6-(97|9A|B7|BA|BE|BF),v1.15,alderlake,core
> +GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
> +GenuineIntel-6-BE,v1.16,alderlaken,core
>  GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
>  GenuineIntel-6-(3D|47),v26,broadwell,core
>  GenuineIntel-6-56,v23,broadwellde,core
> --
> 2.25.1
>