Re: [PATCH v6 07/11] arm64: dts: mt7986: add usb related device nodes

[Chunfeng Yun (云春峰)]

On Fri, 2022-11-18 at 20:01 +0100, Frank Wunderlich wrote:
> From: Sam Shih <sam.shih@xxxxxxxxxxxx>
> 
> This patch adds USB support for MT7986.
> 
> Signed-off-by: Sam Shih <sam.shih@xxxxxxxxxxxx>
> Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
> ---
> changes compared to sams original version:
> - reorder xhci-clocks based on yaml binding
> 
> v5:
>  - update ranges/reg of usb-phy
>  - not added RB from AngeloGioacchino for v4 because of these changes
> 
> v6:
> - remove unused usb regulators
> - remove 3v3 regulator (will be added with emmc-patch)
> ---
>  arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  8 +++
>  arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 55
> ++++++++++++++++++++
>  arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  8 +++
>  3 files changed, 71 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
> b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
> index 006878e3f2b2..828d504a4e48 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
> @@ -140,6 +140,10 @@ &spi1 {
>  	status = "okay";
>  };
>  
> +&ssusb {
> +	status = "okay";
> +};
> +
>  &switch {
>  	ports {
>  		#address-cells = <1>;
> @@ -201,6 +205,10 @@ &uart2 {
>  	status = "okay";
>  };
>  
> +&usb_phy {
> +	status = "okay";
> +};
> +
>  &wifi {
>  	status = "okay";
>  	pinctrl-names = "default", "dbdc";
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> index 29da9b8ed753..c69b8bff7f4a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> @@ -281,6 +281,61 @@ spi1: spi@1100b000 {
>  			status = "disabled";
>  		};
>  
> +		ssusb: usb@11200000 {
> +			compatible = "mediatek,mt7986-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x2e00>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
> +				 <&infracfg CLK_INFRA_IUSB_CK>,
> +				 <&infracfg CLK_INFRA_IUSB_133_CK>,
> +				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
> +				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
> +			clock-names = "sys_ck",
> +				      "ref_ck",
> +				      "mcu_ck",
> +				      "dma_ck",
> +				      "xhci_ck";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>,
> +			       <&u2port1 PHY_TYPE_USB2>;
> +			status = "disabled";
> +		};
> +
> +		usb_phy: t-phy@11e10000 {
> +			compatible = "mediatek,mt7986-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11e10000 0x1700>;
> +			status = "disabled";
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&topckgen
> CLK_TOP_DA_U2_REFSEL>,
> +					 <&topckgen
> CLK_TOP_DA_U2_CK_1P_SEL>;
> +				clock-names = "ref", "da_ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&topckgen
> CLK_TOP_USB3_PHY_SEL>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u2port1: usb-phy@1000 {
> +				reg = <0x1000 0x700>;
> +				clocks = <&topckgen
> CLK_TOP_DA_U2_REFSEL>,
> +					 <&topckgen
> CLK_TOP_DA_U2_CK_1P_SEL>;
> +				clock-names = "ref", "da_ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>  		ethsys: syscon@15000000 {
>  			 #address-cells = <1>;
>  			 #size-cells = <1>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> index 2c7f1d4fb352..cdfc292002cf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
> @@ -167,10 +167,18 @@ &spi1 {
>  	status = "okay";
>  };
>  
> +&ssusb {
> +	status = "okay";
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
>  
> +&usb_phy {
> +	status = "okay";
> +};
> +
>  &wifi {
>  	status = "okay";
>  	pinctrl-names = "default", "dbdc";

Reviewed-by: Chunfeng Yun <chunfeng.yun@xxxxxxxxxxxx>

Thanks a lot