Re: [PATCH v2 5/9] clk: qcom: Add clock driver for SM8550

From: Konrad Dybcio
Date: Wed Nov 23 2022 - 11:12:24 EST

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In reply to: Konrad Dybcio: "Re: [PATCH v2 5/9] clk: qcom: Add clock driver for SM8550"
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On 23.11.2022 17:10, Konrad Dybcio wrote:
>
>
> On 23.11.2022 15:20, Abel Vesa wrote:
>> Add Global Clock controller (GCC) driver for SM8550 SoC,
>> which includes the gcc resets and gdsc.
>>
>> This patch is based on an initial downstream driver.
>>
>> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
>> ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>
> Konrad
I replied and only then noticed, the commit message is a bit vague..
It should mention it is the global clock controller / gcc and not
"a" clock controller. But the code looks good.

Konrad
>>
>> Changes since v1:
>> * Switched to qcom,sm8550-gcc.h instead of qcom,gcc-sm8550.h
>>
>> drivers/clk/qcom/Kconfig | 8 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-sm8550.c | 3396 +++++++++++++++++++++++++++++++++
>> 3 files changed, 3405 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-sm8550.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 76e6dee450d5..e2cfa9c74bcf 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -739,6 +739,14 @@ config SM_GCC_8450
>> Say Y if you want to use peripheral devices such as UART,
>> SPI, I2C, USB, SD/UFS, PCIe etc.
>>
>> +config SM_GCC_8550
>> + tristate "SM8550 Global Clock Controller"
>> + select QCOM_GDSC
>> + help
>> + Support for the global clock controller on SM8550 devices.
>> + Say Y if you want to use peripheral devices such as UART,
>> + SPI, I2C, USB, SD/UFS, PCIe etc.
>> +
>> config SM_GPUCC_6350
>> tristate "SM6350 Graphics Clock Controller"
>> select SM_GCC_6350
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index e6cecf9e0436..06ae671bdea6 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -105,6 +105,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
>> obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
>> obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
>> obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
>> +obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
>> obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
>> obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
>> obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
>> diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
>> new file mode 100644
>> index 000000000000..42987dd55394
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-sm8550.c
>> @@ -0,0 +1,3396 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2022, Linaro Limited
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,sm8550-gcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "clk-regmap-phy-mux.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + DT_BI_TCXO,
>> + DT_SLEEP_CLK,
>> + DT_PCIE_0_PIPE,
>> + DT_PCIE_1_PIPE,
>> + DT_PCIE_1_PHY_AUX,
>> + DT_UFS_PHY_RX_SYMBOL_0,
>> + DT_UFS_PHY_RX_SYMBOL_1,
>> + DT_UFS_PHY_TX_SYMBOL_0,
>> + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
>> +};
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_GCC_GPLL0_OUT_EVEN,
>> + P_GCC_GPLL0_OUT_MAIN,
>> + P_GCC_GPLL4_OUT_MAIN,
>> + P_GCC_GPLL7_OUT_MAIN,
>> + P_GCC_GPLL9_OUT_MAIN,
>> + P_PCIE_0_PIPE_CLK,
>> + P_PCIE_1_PHY_AUX_CLK,
>> + P_PCIE_1_PIPE_CLK,
>> + P_SLEEP_CLK,
>> + P_UFS_PHY_RX_SYMBOL_0_CLK,
>> + P_UFS_PHY_RX_SYMBOL_1_CLK,
>> + P_UFS_PHY_TX_SYMBOL_0_CLK,
>> + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll0 = {
>> + .offset = 0x0,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> + .clkr = {
>> + .enable_reg = 0x52018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpll0",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
>> + { 0x1, 2 },
>> + { }
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
>> + .offset = 0x0,
>> + .post_div_shift = 10,
>> + .post_div_table = post_div_table_gcc_gpll0_out_even,
>> + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
>> + .width = 4,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpll0_out_even",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll4 = {
>> + .offset = 0x4000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> + .clkr = {
>> + .enable_reg = 0x52018,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpll4",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll7 = {
>> + .offset = 0x7000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> + .clkr = {
>> + .enable_reg = 0x52018,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpll7",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gcc_gpll9 = {
>> + .offset = 0x9000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
>> + .clkr = {
>> + .enable_reg = 0x52018,
>> + .enable_mask = BIT(9),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpll9",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_0[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GCC_GPLL0_OUT_MAIN, 1 },
>> + { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_1[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GCC_GPLL0_OUT_MAIN, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .index = DT_SLEEP_CLK },
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_2[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_2[] = {
>> + { .index = DT_BI_TCXO },
>> + { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_3[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GCC_GPLL0_OUT_MAIN, 1 },
>> + { P_GCC_GPLL4_OUT_MAIN, 5 },
>> + { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .hw = &gcc_gpll4.clkr.hw },
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_4[] = {
>> + { P_BI_TCXO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_6[] = {
>> + { P_PCIE_1_PHY_AUX_CLK, 0 },
>> + { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_6[] = {
>> + { .index = DT_PCIE_1_PHY_AUX },
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_8[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GCC_GPLL0_OUT_MAIN, 1 },
>> + { P_GCC_GPLL7_OUT_MAIN, 2 },
>> + { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_8[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .hw = &gcc_gpll7.clkr.hw },
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_9[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GCC_GPLL0_OUT_MAIN, 1 },
>> + { P_GCC_GPLL9_OUT_MAIN, 2 },
>> + { P_GCC_GPLL4_OUT_MAIN, 5 },
>> + { P_GCC_GPLL0_OUT_EVEN, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_9[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .hw = &gcc_gpll9.clkr.hw },
>> + { .hw = &gcc_gpll4.clkr.hw },
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_10[] = {
>> + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
>> + { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_10[] = {
>> + { .index = DT_UFS_PHY_RX_SYMBOL_0 },
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_11[] = {
>> + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
>> + { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_11[] = {
>> + { .index = DT_UFS_PHY_RX_SYMBOL_1 },
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_12[] = {
>> + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
>> + { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_12[] = {
>> + { .index = DT_UFS_PHY_TX_SYMBOL_0 },
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_13[] = {
>> + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
>> + { P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_13[] = {
>> + { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
>> + .reg = 0x6b070,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_pipe_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_PCIE_0_PIPE,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_regmap_phy_mux_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
>> + .reg = 0x8d094,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_6,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_6,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
>> + .reg = 0x8d078,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_pipe_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .index = DT_PCIE_1_PIPE,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_regmap_phy_mux_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
>> + .reg = 0x77064,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_10,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
>> + .parent_data = gcc_parent_data_10,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_10),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
>> + .reg = 0x770e0,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_11,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
>> + .parent_data = gcc_parent_data_11,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_11),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
>> + .reg = 0x77054,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_12,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
>> + .parent_data = gcc_parent_data_12,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_12),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
>> + .reg = 0x3906c,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_13,
>> + .clkr = {
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_pipe_clk_src",
>> + .parent_data = gcc_parent_data_13,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_13),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp1_clk_src = {
>> + .cmd_rcgr = 0x64004,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_1,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp1_clk_src",
>> + .parent_data = gcc_parent_data_1,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp2_clk_src = {
>> + .cmd_rcgr = 0x65004,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_1,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp2_clk_src",
>> + .parent_data = gcc_parent_data_1,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp3_clk_src = {
>> + .cmd_rcgr = 0x66004,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_1,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp3_clk_src",
>> + .parent_data = gcc_parent_data_1,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>> + .cmd_rcgr = 0x6b074,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_aux_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
>> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
>> + .cmd_rcgr = 0x6b058,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_phy_rchng_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
>> + .cmd_rcgr = 0x8d07c,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_aux_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
>> + .cmd_rcgr = 0x8d060,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_phy_rchng_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
>> + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pdm2_clk_src = {
>> + .cmd_rcgr = 0x33010,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pdm2_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
>> + .cmd_rcgr = 0x17008,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s0_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
>> + .cmd_rcgr = 0x17024,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s1_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
>> + .cmd_rcgr = 0x17040,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
>> + .cmd_rcgr = 0x1705c,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s3_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
>> + .cmd_rcgr = 0x17078,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s4_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
>> + .cmd_rcgr = 0x17094,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s5_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
>> + .cmd_rcgr = 0x170b0,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s6_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
>> + .cmd_rcgr = 0x170cc,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s7_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
>> + .cmd_rcgr = 0x170e8,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s8_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
>> + .cmd_rcgr = 0x17104,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s9_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
>> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
>> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
>> + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
>> + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
>> + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s0_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
>> + .cmd_rcgr = 0x18010,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s1_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
>> + .cmd_rcgr = 0x18148,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = {
>> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
>> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
>> + .cmd_rcgr = 0x18280,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s3_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
>> + .cmd_rcgr = 0x183b8,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s4_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
>> + .cmd_rcgr = 0x184f0,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s5_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
>> + .cmd_rcgr = 0x18628,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s6_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
>> + .cmd_rcgr = 0x18760,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
>> + .name = "gcc_qupv3_wrap1_s7_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
>> + .cmd_rcgr = 0x18898,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s0_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
>> + .cmd_rcgr = 0x1e010,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s1_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
>> + .cmd_rcgr = 0x1e148,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s2_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
>> + .cmd_rcgr = 0x1e280,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s3_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
>> + .cmd_rcgr = 0x1e3b8,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s4_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
>> + .cmd_rcgr = 0x1e4f0,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s5_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
>> + .cmd_rcgr = 0x1e628,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {
>> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
>> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
>> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
>> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
>> + F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
>> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
>> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
>> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
>> + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
>> + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
>> + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
>> + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
>> + F(125000000, P_GCC_GPLL0_OUT_MAIN, 1, 5, 24),
>> + { }
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s6_clk_src",
>> + .parent_data = gcc_parent_data_8,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_8),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
>> + .cmd_rcgr = 0x1e760,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_8,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
>> +};
>> +
>> +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
>> + .name = "gcc_qupv3_wrap2_s7_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> +};
>> +
>> +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
>> + .cmd_rcgr = 0x1e898,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s2_clk_src,
>> + .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
>> + F(400000, P_BI_TCXO, 12, 1, 4),
>> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
>> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
>> + .cmd_rcgr = 0x14018,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_9,
>> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_apps_clk_src",
>> + .parent_data = gcc_parent_data_9,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
>> + F(400000, P_BI_TCXO, 12, 1, 4),
>> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
>> + .cmd_rcgr = 0x16018,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc4_apps_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
>> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
>> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
>> + .cmd_rcgr = 0x77030,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_axi_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
>> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>> + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
>> + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
>> + .cmd_rcgr = 0x77080,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_3,
>> + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ice_core_clk_src",
>> + .parent_data = gcc_parent_data_3,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
>> + F(9600000, P_BI_TCXO, 2, 0, 0),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
>> + .cmd_rcgr = 0x770b4,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_4,
>> + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_4,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_4),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
>> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
>> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
>> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
>> + .cmd_rcgr = 0x77098,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_unipro_core_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
>> + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
>> + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
>> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
>> + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
>> + .cmd_rcgr = 0x3902c,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_master_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
>> + .cmd_rcgr = 0x39044,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_mock_utmi_clk_src",
>> + .parent_data = gcc_parent_data_0,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>> + .cmd_rcgr = 0x39070,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
>> + .reg = 0x3905c,
>> + .shift = 0,
>> + .width = 4,
>> + .clkr.hw.init = &(struct clk_init_data) {
>> + .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_regmap_div_ro_ops,
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
>> + .halt_reg = 0x1003c,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x1003c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(12),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_noc_pcie_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>> + .halt_reg = 0x770e4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x770e4,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x770e4,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_ufs_phy_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
>> + .halt_reg = 0x770e4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x770e4,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x770e4,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
>> + .halt_reg = 0x3908c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x3908c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x3908c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_aggre_usb3_prim_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_boot_rom_ahb_clk = {
>> + .halt_reg = 0x38004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x38004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(10),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_boot_rom_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_hf_axi_clk = {
>> + .halt_reg = 0x26010,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x26010,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x26010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_camera_sf_axi_clk = {
>> + .halt_reg = 0x2601c,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x2601c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x2601c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_camera_sf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
>> + .halt_reg = 0x10028,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x10028,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(20),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
>> + .halt_reg = 0x39088,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x39088,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x39088,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cfg_noc_usb3_prim_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
>> + .halt_reg = 0x10030,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x10030,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(6),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_cnoc_pcie_sf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ddrss_gpu_axi_clk = {
>> + .halt_reg = 0x71154,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x71154,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x71154,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ddrss_gpu_axi_clk",
>> + .ops = &clk_branch2_aon_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
>> + .halt_reg = 0x1004c,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x1004c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(19),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ddrss_pcie_sf_qtb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_disp_hf_axi_clk = {
>> + .halt_reg = 0x2700c,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x2700c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x2700c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_disp_hf_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp1_clk = {
>> + .halt_reg = 0x64000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x64000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp2_clk = {
>> + .halt_reg = 0x65000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x65000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gp3_clk = {
>> + .halt_reg = 0x66000,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x66000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gp3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gp3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(15),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_gpll0_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(16),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_gpll0_div_clk_src",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_gpll0_out_even.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
>> + .halt_reg = 0x71010,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x71010,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x71010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_memnoc_gfx_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
>> + .halt_reg = 0x71018,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x71018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_gpu_snoc_dvm_gfx_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_aux_clk = {
>> + .halt_reg = 0x6b03c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(3),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
>> + .halt_reg = 0x6b038,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x6b038,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(2),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_cfg_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
>> + .halt_reg = 0x6b02c,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x6b02c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_mstr_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
>> + .halt_reg = 0x6b054,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(22),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_phy_rchng_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_pipe_clk = {
>> + .halt_reg = 0x6b048,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_pipe_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
>> + .halt_reg = 0x6b020,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x6b020,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_slv_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
>> + .halt_reg = 0x6b01c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(5),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_0_slv_q2a_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_aux_clk = {
>> + .halt_reg = 0x8d038,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(29),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
>> + .halt_reg = 0x8d034,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x8d034,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(28),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_cfg_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
>> + .halt_reg = 0x8d028,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x8d028,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(27),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_mstr_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_phy_aux_clk = {
>> + .halt_reg = 0x8d044,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(24),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_phy_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
>> + .halt_reg = 0x8d05c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(23),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_phy_rchng_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_pipe_clk = {
>> + .halt_reg = 0x8d050,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(30),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_pipe_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_slv_axi_clk = {
>> + .halt_reg = 0x8d01c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x8d01c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(26),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_slv_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
>> + .halt_reg = 0x8d018,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(25),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pcie_1_slv_q2a_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm2_clk = {
>> + .halt_reg = 0x3300c,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x3300c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_pdm2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm_ahb_clk = {
>> + .halt_reg = 0x33004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x33004,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x33004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_pdm_xo4_clk = {
>> + .halt_reg = 0x33008,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x33008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_pdm_xo4_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
>> + .halt_reg = 0x26008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x26008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x26008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_camera_nrt_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
>> + .halt_reg = 0x2600c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x2600c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x2600c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_camera_rt_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_disp_ahb_clk = {
>> + .halt_reg = 0x27008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x27008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x27008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_disp_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_gpu_ahb_clk = {
>> + .halt_reg = 0x71008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x71008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x71008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_gpu_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_pcie_ahb_clk = {
>> + .halt_reg = 0x6b018,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x6b018,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(11),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_pcie_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
>> + .halt_reg = 0x32014,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x32014,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x32014,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_video_cv_cpu_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
>> + .halt_reg = 0x32008,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x32008,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x32008,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_video_cvp_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
>> + .halt_reg = 0x32010,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x32010,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x32010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_video_v_cpu_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
>> + .halt_reg = 0x3200c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x3200c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x3200c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qmip_video_vcodec_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_core_clk = {
>> + .halt_reg = 0x23144,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(8),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_core_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s0_clk = {
>> + .halt_reg = 0x17004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(10),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s1_clk = {
>> + .halt_reg = 0x17020,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(11),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s2_clk = {
>> + .halt_reg = 0x1703c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(12),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s3_clk = {
>> + .halt_reg = 0x17058,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(13),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s4_clk = {
>> + .halt_reg = 0x17074,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(14),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s4_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s4_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s5_clk = {
>> + .halt_reg = 0x17090,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(15),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s5_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s5_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s6_clk = {
>> + .halt_reg = 0x170ac,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(16),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s6_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s6_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s7_clk = {
>> + .halt_reg = 0x170c8,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(17),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s7_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s7_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s8_clk = {
>> + .halt_reg = 0x170e4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(14),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s8_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s8_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s9_clk = {
>> + .halt_reg = 0x17100,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(15),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s9_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_i2c_s9_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {
>> + .halt_reg = 0x23140,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x23140,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_i2c_s_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
>> + .halt_reg = 0x23294,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(18),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_core_2x_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_core_clk = {
>> + .halt_reg = 0x23284,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(19),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_core_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
>> + .halt_reg = 0x18004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(22),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
>> + .halt_reg = 0x1813c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(23),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
>> + .halt_reg = 0x18274,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(24),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
>> + .halt_reg = 0x183ac,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(25),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
>> + .halt_reg = 0x184e4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(26),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s4_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
>> + .halt_reg = 0x1861c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(27),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s5_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
>> + .halt_reg = 0x18754,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(28),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s6_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
>> + .halt_reg = 0x1888c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(16),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap1_s7_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
>> + .halt_reg = 0x23004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(3),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_core_2x_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_core_clk = {
>> + .halt_reg = 0x233d4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_core_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
>> + .halt_reg = 0x1e004,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
>> + .halt_reg = 0x1e13c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(5),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
>> + .halt_reg = 0x1e274,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(6),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s2_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
>> + .halt_reg = 0x1e3ac,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s3_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
>> + .halt_reg = 0x1e4e4,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(8),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s4_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
>> + .halt_reg = 0x1e61c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(9),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s5_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
>> + .halt_reg = 0x1e754,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(10),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s6_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
>> + .halt_reg = 0x1e88c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(17),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap2_s7_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
>> + .halt_reg = 0x2327c,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x2327c,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(20),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_1_m_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
>> + .halt_reg = 0x23280,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x23280,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52008,
>> + .enable_mask = BIT(21),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_1_s_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
>> + .halt_reg = 0x233cc,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x233cc,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(2),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_2_m_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
>> + .halt_reg = 0x233d0,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x233d0,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x52010,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_qupv3_wrap_2_s_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc2_ahb_clk = {
>> + .halt_reg = 0x14010,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x14010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc2_apps_clk = {
>> + .halt_reg = 0x14004,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x14004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc2_apps_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc4_ahb_clk = {
>> + .halt_reg = 0x16010,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x16010,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc4_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_sdcc4_apps_clk = {
>> + .halt_reg = 0x16004,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x16004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_sdcc4_apps_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_ahb_clk = {
>> + .halt_reg = 0x77024,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77024,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77024,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ahb_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_axi_clk = {
>> + .halt_reg = 0x77018,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77018,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_axi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
>> + .halt_reg = 0x77018,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77018,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77018,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_axi_hw_ctl_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_ice_core_clk = {
>> + .halt_reg = 0x77074,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77074,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77074,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ice_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
>> + .halt_reg = 0x77074,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77074,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77074,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>> + .halt_reg = 0x770b0,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x770b0,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x770b0,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_phy_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
>> + .halt_reg = 0x770b0,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x770b0,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x770b0,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>> + .halt_reg = 0x7702c,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x7702c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
>> + .halt_reg = 0x770cc,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x770cc,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_rx_symbol_1_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
>> + .halt_reg = 0x77028,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x77028,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_tx_symbol_0_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
>> + .halt_reg = 0x77068,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77068,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77068,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_unipro_core_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
>> + .halt_reg = 0x77068,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x77068,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x77068,
>> + .enable_mask = BIT(1),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_master_clk = {
>> + .halt_reg = 0x39018,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x39018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_master_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
>> + .halt_reg = 0x39028,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x39028,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_mock_utmi_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb30_prim_sleep_clk = {
>> + .halt_reg = 0x39024,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x39024,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb30_prim_sleep_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
>> + .halt_reg = 0x39060,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x39060,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
>> + .halt_reg = 0x39064,
>> + .halt_check = BRANCH_HALT,
>> + .clkr = {
>> + .enable_reg = 0x39064,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_com_aux_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
>> + .halt_reg = 0x39068,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .hwcg_reg = 0x39068,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x39068,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb3_prim_phy_pipe_clk",
>> + .parent_data = &(const struct clk_parent_data){
>> + .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_video_axi0_clk = {
>> + .halt_reg = 0x32018,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x32018,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x32018,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_video_axi0_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_video_axi1_clk = {
>> + .halt_reg = 0x32024,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .hwcg_reg = 0x32024,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x32024,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_video_axi1_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct gdsc pcie_0_gdsc = {
>> + .gdscr = 0x6b004,
>> + .pd = {
>> + .name = "pcie_0_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc pcie_0_phy_gdsc = {
>> + .gdscr = 0x6c000,
>> + .pd = {
>> + .name = "pcie_0_phy_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc pcie_1_gdsc = {
>> + .gdscr = 0x8d004,
>> + .pd = {
>> + .name = "pcie_1_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc pcie_1_phy_gdsc = {
>> + .gdscr = 0x8e000,
>> + .pd = {
>> + .name = "pcie_1_phy_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc ufs_phy_gdsc = {
>> + .gdscr = 0x77004,
>> + .pd = {
>> + .name = "ufs_phy_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc ufs_mem_phy_gdsc = {
>> + .gdscr = 0x9e000,
>> + .pd = {
>> + .name = "ufs_mem_phy_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc usb30_prim_gdsc = {
>> + .gdscr = 0x39004,
>> + .pd = {
>> + .name = "usb30_prim_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct gdsc usb3_phy_gdsc = {
>> + .gdscr = 0x50018,
>> + .pd = {
>> + .name = "usb3_phy_gdsc",
>> + },
>> + .poll_timeout = 1500,
>> + .pwrsts = PWRSTS_OFF_ON,
>> + .flags = POLL_CFG_GDSCR,
>> +};
>> +
>> +static struct clk_regmap *gcc_sm8550_clocks[] = {
>> + [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
>> + [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
>> + [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
>> + [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
>> + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
>> + [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
>> + [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
>> + [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
>> + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
>> + [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
>> + [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
>> + [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
>> + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
>> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
>> + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
>> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
>> + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
>> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
>> + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
>> + [GCC_GPLL0] = &gcc_gpll0.clkr,
>> + [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
>> + [GCC_GPLL4] = &gcc_gpll4.clkr,
>> + [GCC_GPLL7] = &gcc_gpll7.clkr,
>> + [GCC_GPLL9] = &gcc_gpll9.clkr,
>> + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
>> + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
>> + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
>> + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
>> + [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
>> + [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
>> + [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
>> + [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
>> + [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
>> + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
>> + [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
>> + [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
>> + [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
>> + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
>> + [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
>> + [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
>> + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
>> + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
>> + [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
>> + [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
>> + [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
>> + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
>> + [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
>> + [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
>> + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
>> + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
>> + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
>> + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
>> + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
>> + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
>> + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
>> + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
>> + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
>> + [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
>> + [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
>> + [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
>> + [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
>> + [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
>> + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
>> + [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr,
>> + [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr,
>> + [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr,
>> + [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr,
>> + [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr,
>> + [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr,
>> + [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr,
>> + [GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr,
>> + [GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr,
>> + [GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr,
>> + [GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr,
>> + [GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr,
>> + [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr,
>> + [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
>> + [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
>> + [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
>> + [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
>> + [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
>> + [GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
>> + [GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
>> + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
>> + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
>> + [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
>> + [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
>> + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
>> + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
>> + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
>> + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
>> + [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
>> + [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
>> + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
>> + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
>> + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
>> + [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
>> + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
>> + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
>> + [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
>> + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
>> + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
>> + [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
>> + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
>> + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
>> + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
>> + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
>> + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
>> + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
>> + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
>> + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
>> + [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
>> + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
>> + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
>> + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
>> + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
>> + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
>> + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
>> + [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
>> + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
>> + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
>> + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
>> + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
>> + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
>> + [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
>> +};
>> +
>> +static const struct qcom_reset_map gcc_sm8550_resets[] = {
>> + [GCC_CAMERA_BCR] = { 0x26000 },
>> + [GCC_DISPLAY_BCR] = { 0x27000 },
>> + [GCC_GPU_BCR] = { 0x71000 },
>> + [GCC_PCIE_0_BCR] = { 0x6b000 },
>> + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
>> + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
>> + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
>> + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
>> + [GCC_PCIE_1_BCR] = { 0x8d000 },
>> + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
>> + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
>> + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
>> + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
>> + [GCC_PCIE_PHY_BCR] = { 0x6f000 },
>> + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
>> + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
>> + [GCC_PDM_BCR] = { 0x33000 },
>> + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
>> + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
>> + [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
>> + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
>> + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
>> + [GCC_SDCC2_BCR] = { 0x14000 },
>> + [GCC_SDCC4_BCR] = { 0x16000 },
>> + [GCC_UFS_PHY_BCR] = { 0x77000 },
>> + [GCC_USB30_PRIM_BCR] = { 0x39000 },
>> + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
>> + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
>> + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
>> + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
>> + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
>> + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
>> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
>> + [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
>> + [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
>> + [GCC_VIDEO_BCR] = { 0x32000 },
>> +};
>> +
>> +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
>> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
>> +};
>> +
>> +static struct gdsc *gcc_sm8550_gdscs[] = {
>> + [PCIE_0_GDSC] = &pcie_0_gdsc,
>> + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
>> + [PCIE_1_GDSC] = &pcie_1_gdsc,
>> + [PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
>> + [UFS_PHY_GDSC] = &ufs_phy_gdsc,
>> + [UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc,
>> + [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
>> + [USB3_PHY_GDSC] = &usb3_phy_gdsc,
>> +};
>> +
>> +static const struct regmap_config gcc_sm8550_regmap_config = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .max_register = 0x1f41f0,
>> + .fast_io = true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_sm8550_desc = {
>> + .config = &gcc_sm8550_regmap_config,
>> + .clks = gcc_sm8550_clocks,
>> + .num_clks = ARRAY_SIZE(gcc_sm8550_clocks),
>> + .resets = gcc_sm8550_resets,
>> + .num_resets = ARRAY_SIZE(gcc_sm8550_resets),
>> + .gdscs = gcc_sm8550_gdscs,
>> + .num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
>> +};
>> +
>> +static const struct of_device_id gcc_sm8550_match_table[] = {
>> + { .compatible = "qcom,sm8550-gcc" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_sm8550_match_table);
>> +
>> +static int gcc_sm8550_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> + int ret;
>> +
>> + regmap = qcom_cc_map(pdev, &gcc_sm8550_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> +
>> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> + ARRAY_SIZE(gcc_dfs_clocks));
>> + if (ret)
>> + return ret;
>> +
>> + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
>> + regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
>> +
>> + /*
>> + * Keep the critical clock always-On
>> + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
>> + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
>> + * gcc_video_xo_clk
>> + */
>> + regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
>> + regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0));
>> +
>> + /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
>> + regmap_write(regmap, 0x52024, 0x0);
>> +
>> + return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap);
>> +}
>> +
>> +static struct platform_driver gcc_sm8550_driver = {
>> + .probe = gcc_sm8550_probe,
>> + .driver = {
>> + .name = "gcc-sm8550",
>> + .of_match_table = gcc_sm8550_match_table,
>> + },
>> +};
>> +
>> +static int __init gcc_sm8550_init(void)
>> +{
>> + return platform_driver_register(&gcc_sm8550_driver);
>> +}
>> +subsys_initcall(gcc_sm8550_init);
>> +
>> +static void __exit gcc_sm8550_exit(void)
>> +{
>> + platform_driver_unregister(&gcc_sm8550_driver);
>> +}
>> +module_exit(gcc_sm8550_exit);
>> +
>> +MODULE_DESCRIPTION("QTI GCC SM8550 Driver");
>> +MODULE_LICENSE("GPL");

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