Re: [PATCH v2,3/3] arm64: dts: mt8195: Add video decoder node

[Nícolas F. R. A. Prado]

On Thu, Nov 10, 2022 at 06:28:34PM +0800, Yunfei Dong wrote:
> Add video decoder node to mt8195 device tree.
> 
> Signed-off-by: Yunfei Dong <yunfei.dong@xxxxxxxxxxxx>
> ---
> Compared with v1:
> - add description in yaml, and remove /* ... */ for each reg.
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 63 ++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..3ef7eef02415 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1874,6 +1874,69 @@
>  			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
>  		};
>  
> +		video-codec@18000000 {
> +			compatible = "mediatek,mt8195-vcodec-dec";
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
> +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

Hi,

similarly to what I've commented for the mt8192 node [1], having dma-ranges
on this node causes IOMMU faults on the latest next. Since the iommu is already
used in this node, please drop the dma-ranges property.

The binding will also need updating to remove this property (given it was marked
as required), so please include that change in either your or Allen's series.

+cc Allen

[1] https://lore.kernel.org/all/20221118141039.y2ap7dzdp26ih2la@notapiano

Thanks,
Nícolas

> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			reg = <0 0x18000000 0 0x1000>,
> +			      <0 0x18004000 0 0x1000>;
> +			ranges = <0 0 0 0x18000000 0 0x26000>;
> +			clocks = <&topckgen CLK_TOP_VDEC>,
> +			         <&topckgen CLK_TOP_UNIVPLL_D4>;
> +			clock-names = "vdec-sel", "top";
> +			assigned-clocks = <&topckgen CLK_TOP_VDEC>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +
> +			vcodec-lat-soc@2000 {
> +				compatible = "mediatek,mtk-vcodec-lat-soc";
> +				reg = <0 0x2000 0 0x800>;
> +				iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
> +					 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
> +				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
> +				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
> +				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> +			};
> +
> +			vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0 0x10000 0 0x800>;
> +				interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
> +				clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>;
> +				clock-names = "vdec-soc-vdec", "vdec-soc-lat";
> +				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> +			};
> +
> +			vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;
> +				interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
> +					 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
> +				clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LAT>;
> +				clock-names = "vdec-vdec", "vdec-lat";
> +				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> +			};
> +		};
> +
>  		larb24: larb@1800d000 {
>  			compatible = "mediatek,mt8195-smi-larb";
>  			reg = <0 0x1800d000 0 0x1000>;
> -- 
> 2.18.0
> 
> 
>