Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes

[Johan Hovold]

On Wed, Nov 16, 2022 at 02:51:11PM +0200, Abel Vesa wrote:
> Add UFS host controller and PHY nodes.
> 
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..27ce382cb594 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		ufs_mem_phy: phy@1d80000 {
> +			compatible = "qcom,sm8550-qmp-ufs-phy";

Where's the corresponding binding update?

> +			reg = <0x0 0x01d80000 0x0 0x200>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			clock-names = "ref", "qref";
> +			clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> +				 <&tcsr TCSR_UFS_CLKREF_EN>;
> +
> +			power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
> +			status = "disabled";
> +
> +			ufs_mem_phy_lanes: phy@1d80400 {
> +				reg = <0x0 0x01d81000 0x0 0x134>,
> +				      <0x0 0x01d81200 0x0 0x3d8>,
> +				      <0x0 0x01d80400 0x0 0x258>,
> +				      <0x0 0x01d81800 0x0 0x134>,
> +				      <0x0 0x01d81a00 0x0 0x3d8>;
> +				#phy-cells = <0>;
> +			};

This should be converted to use the new binding scheme which drops the
child node and individual register descriptions (cf. sc8280xp).

> +		};

Johan